Sorkin, Gregory B. 
ORCID: 0000-0003-4935-7820
(1987)
Asymptotically perfect trivial global routing: a stochastic analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 6 (5).
pp. 820-827.
ISSN 0278-0070
Abstract
A two-dimensional stochastic model of the global wiring of a VLSI chip in a standard-cell or sea-of-gates design style is defined; prominent in the model is the property that the probability of connecting two pins is solely a function of the distance between the cells containing them. It is also assumed that each net consists of just two pins. A lower bound is placed on the expected size of the chip with the best possible wiring. An upper bound is placed on the expected size of the chip with a trivial (all randomly-oriented "L"s) wiring scheme. If the chip size is m rows by n columns and the size of the average row is /overbar μ/ the sizes of the trivial and perfect routings, expressed as a fraction of the size of the perfect routing, approaches 0 as √2 log (n)/ /overbar μ/ It is also shown that with probability at least 1 - ∊ size increase is no more than √2 log (mn/∊/ /overbar μ/.
| Item Type: | Article |
|---|---|
| Official URL: | http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?pun... |
| Additional Information: | © 1987 IEEE Council on Electronic Design Automation |
| Divisions: | Management |
| Subjects: | Q Science > QA Mathematics > QA75 Electronic computers. Computer science |
| Date Deposited: | 13 Apr 2011 15:05 |
| Last Modified: | 13 Sep 2024 20:55 |
| URI: | http://eprints.lse.ac.uk/id/eprint/35567 |
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